The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Jan. 02, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yi-Hsiu Chen, Hsinchu, TW;

Chia-Fang Tsai, Hsinchu, TW;

Ming-Yun Liao, Taoyuan City, TW;

Yu-Chian Chiang, Kaohsiung City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 74/15 (2026.01); H10W 80/00 (2026.01);
U.S. Cl.
CPC ...
H10W 74/121 (2026.01); H10W 72/942 (2026.01); H10W 74/014 (2026.01); H10W 74/019 (2026.01); H10W 90/00 (2026.01); H10W 72/01931 (2026.01); H10W 72/01935 (2026.01); H10W 72/01938 (2026.01); H10W 72/252 (2026.01); H10W 72/29 (2026.01); H10W 72/923 (2026.01); H10W 72/941 (2026.01); H10W 72/9413 (2026.01); H10W 72/944 (2026.01); H10W 72/951 (2026.01); H10W 72/952 (2026.01); H10W 72/963 (2026.01); H10W 72/967 (2026.01); H10W 74/15 (2026.01); H10W 80/211 (2026.01); H10W 80/327 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/734 (2026.01); H10W 90/792 (2026.01);
Abstract

An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include a first die having a first substrate and a first through via extending through the first substrate, a first gap-fill layer along a sidewall of the first substrate, an isolation layer on a surface of the first substrate and a surface of the first gap-fill layer, a first bonding layer over the isolation layer, and a first bonding pad in the first bonding layer. The isolation layer may overlap an interface between the sidewall of the first substrate and a sidewall of the first gap-fill layer, and may extend on sidewalls of the first through via.


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