Santa Clara, CA, United States of America

Yoshiyuki Miyayama

This inventor holds 51 USPTO granted patents, primarily in Superscalar Microprocessors (CPC class 7122). Top assignees: Seiko Epson Corporation, Transmeta Corporation, S-Mos Systems, Inc.. Active years: 1994-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoshiyuki Miyayama. Retrieved from https://idiyas.com/inventor/yoshiyuki-miyayama

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 60.8

Average Co-Inventor Count = 5.4

ph-index = 22

Forward Citations = 1,344(Granted Patents)

Forward Citations (Not Self Cited) = 1,160(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Suwa, JP (1999 - 2006)
  • Santa Clara, CA (US) (1994 - 2011)
  • Nagano-ken, JP (2005 - 2011)

Company Filing History:


Years Active: 1994-2011

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Areas of Expertise:
Superscalar Microprocessor
Out-Of-Order Execution
Instruction Translation
Concurrent Results Distribution
Microcomputer
Data Processing Circuit
Debugging System
Semiconductor Device
Electronic Equipment
Pin Compatibility
High-Performance Computing
51 patents (USPTO):Explore Patents

Title: Innovations of Yoshiyuki Miyayama: A Pioneer in Microprocessor Technology

Introduction: Yoshiyuki Miyayama is a notable inventor based in Santa Clara, CA, who has made significant contributions to the field of microprocessor technology. With a remarkable portfolio of 51 patents to his name, Miyayama has established himself as a leading figure in innovation, particularly within the realm of computer architecture.

Latest Patents: Among his latest patents, two stand out for their groundbreaking approaches to handling operations in superscalar microprocessors. The first patent, titled "System and method for handling load and/or store operations in a superscalar microprocessor," provides a comprehensive system for managing load and store operations essential for reading from and writing to memory in a superscalar RISC architecture. This invention emphasizes the importance of executing load requests out of order to enhance the speed at which load data is retrieved for the instruction execution unit. Key tasks of the load store unit involve managing out-of-order cache requests, detecting address collisions, and ensuring proper data alignment.

The second relevant patent, "High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution," introduces an advanced microprocessor architecture that facilitates concurrent execution of multiple instructions. This architecture efficiently employs a unified instruction scheduler to optimize processing by coordinating across various functional units tailored for specific computational tasks.

Career Highlights: Miyayama's illustrious career includes tenure at prestigious companies, notably Seiko Epson Corporation. His innovative work has been pivotal in enhancing microprocessor capabilities, particularly in the context of RISC architecture. This has contributed significantly to advancements in computer processing efficiency.

Collaborations: Throughout his career, Miyayama has collaborated with esteemed colleagues, including Johannes Wang and Le Trong Nguyen. Their collective efforts have fostered an environment of innovation, driving forward the boundaries of microprocessor design and functionality.

Conclusion: Yoshiyuki Miyayama's extensive portfolio and collaborative achievements underscore his pivotal role as an inventor in the tech industry. His contributions continue to impact the development of high-performance computing systems, reinforcing his status as a leading innovator in the field of microprocessor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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