Suwon-si, South Korea

Yoonjoong Kim

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Samsung Electronics Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoonjoong Kim. Retrieved from https://idiyas.com/inventor/yoonjoong-kim-spbi92ci

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Yoonjoong Kim and Semiconductor Device Innovation.

Introduction

Yoonjoong Kim is an inventor based in Suwon-si, South Korea. His listed patent work concerns semiconductor device structures, including channel structures, impurity regions, and gate structures. He is associated with Samsung Electronics Ltd.

Latest Patents

Kim is listed as an inventor on 1 patent, titled “Semiconductor Device with Channel Structures and Impurity Region Structures.” The patent describes a device with first and second channel structures on a substrate, impurity region structures positioned between them, and gate structures arranged between the impurity regions. The first channel structures are wider than the second channel structures. The impurity region volumes are also differentiated: the first is largest, the second is smallest, and the third falls between them. These structural variations describe an approach to configuring semiconductor devices.

Career Highlights

The available information identifies Kim’s work with Samsung Electronics Ltd. and records one patent associated with him. The patent focuses on semiconductor device architecture and the arrangement of channel, impurity, and gate structures.

Collaborations

Taeyong Kwon is identified as Kim’s coworker. The provided information does not specify their roles or describe a particular joint project.

Conclusion

Yoonjoong Kim’s listed patent reflects work on semiconductor device structures, with a focus on varying channel widths and impurity region volumes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…