Hsinchu, Taiwan

Ying-Ju Wu

This inventor holds 1 USPTO granted patent and 3 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ying-Ju Wu. Retrieved from https://idiyas.com/inventor/ying-ju-wu-9n75lyf1

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Ying-Ju Wu: Semiconductor Invention in Hsinchu

Introduction

Ying-Ju Wu is an inventor based in Hsinchu, Taiwan. His patent work concerns semiconductor device fabrication and the integration of a metal-insulator-metal capacitor into a passivation layer. He is associated with Taiwan Semiconductor Manufacturing Company Limited.

Latest Patents

Wu is credited with 1 patent, titled “Embedding a Metal-Insulator-Metal Capacitor in a Passivation Layer.” The invention describes forming a passivation layer over an interconnect structure and etching an opening into it. A first conductive layer and an insulator layer are deposited so that each partially fills the opening. A second conductive layer is then deposited to completely fill the opening. Conductive structures are formed to electrically couple to the first and second conductive layers, respectively.

Career Highlights

Wu’s listed patent reflects work on integrating capacitor structures within semiconductor passivation layers. The described process uses layered conductive and insulating materials to form the capacitor within an opening above an interconnect structure.

Collaborations

Wu’s listed coworker is Tzu-Ting Liu. The available information identifies both inventors in connection with the patent.

Conclusion

Ying-Ju Wu’s patent documents a semiconductor fabrication approach for embedding a metal-insulator-metal capacitor in a passivation layer, highlighting his contribution to integrated device design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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