Milpitas, CA, United States of America

Yi-Jung Liu

USPTO Granted Patents = 2 

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2023-2024

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2 patents (USPTO):Explore Patents

Title: Yi-Jung Liu: Innovator in Package Structure Technology

Introduction

Yi-Jung Liu is a notable inventor based in Milpitas, CA (US). He has made significant contributions to the field of package structure technology, holding a total of 2 patents. His innovative methods have advanced the way package structures are formed, showcasing his expertise and creativity in engineering.

Latest Patents

Yi-Jung Liu's latest patents focus on a method of forming a package structure. This method includes several critical steps: an etching step, a laser step, a plating step, and a singulation step. In the etching step, a plurality of cutting streets of a leadframe are etched. The laser step involves removing a plastic package material covering each of the cutting streets via a laser beam. During the plating step, a plurality of plating surfaces are disposed on various areas of the leadframe that lack the plastic package material. Finally, in the singulation step, the cutting streets of the leadframe are cut to form the package structure.

Career Highlights

Yi-Jung Liu is currently employed at Integrated Silicon Solution Incorporated, where he continues to develop innovative solutions in semiconductor packaging. His work has been instrumental in enhancing the efficiency and effectiveness of package structures in the industry.

Collaborations

Some of his coworkers include Cheng-Fu Yu and Kai-Jih Shih, who contribute to the collaborative environment that fosters innovation at Integrated Silicon Solution Incorporated.

Conclusion

Yi-Jung Liu's contributions to package structure technology reflect his dedication to innovation and excellence in engineering. His patents and work at Integrated Silicon Solution Incorporated highlight his role as a key player in advancing semiconductor packaging methods.

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