Taichung, Taiwan

Yeo-Sin Lin

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2024.

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2024

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1 patent (USPTO):Explore Patents

Title: Yeo-Sin Lin: Innovator in Electrical Cleaning Tools

Introduction

Yeo-Sin Lin is an inventor based in Taichung, Taiwan. He has made significant contributions to the field of electrical cleaning tools, particularly in the context of wafer polishing systems. His innovative approach focuses on enhancing the efficiency and effectiveness of wafer processing.

Latest Patent Applications

Yeo-Sin Lin's notable patent application is titled "ELECTRICAL CLEANING TOOL FOR WAFER POLISHING TOOL SYSTEM." This application describes a process tool that includes a polishing pad on the top surface of a wafer platen. A wafer carrier is designed to hold a wafer over the polishing pad. Additionally, a slurry dispenser is configured to dispense an abrasive slurry containing charged abrasive particles with a first polarity onto the polishing pad. The invention features a first conductive rod within the wafer platen, coupled to a first voltage supply, and a wafer roller that supports the wafer. A first wafer brush is positioned beside the wafer roller, with a second conductive rod within the first wafer brush, connected to a second voltage supply. The first voltage supply applies a first charge with a second polarity, opposite the first polarity, to the first conductive rod, while the second voltage supply applies a second charge with the same second polarity to the second conductive rod.

Conclusion

Yeo-Sin Lin's work in developing electrical cleaning tools for wafer polishing systems showcases his innovative spirit and dedication to advancing technology in this field. His contributions, although not yet resulting in granted patents, reflect a commitment to improving wafer processing techniques.

Profile summary based on public USPTO records.
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