Kanagawa, Japan

Yasuo Kobayashi

This inventor holds 5 USPTO granted patents and 1 published patent application. Top assignees: Fuji Electric Co., Ltd., Renesas Electronics Corporation. Active years: 1995-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yasuo Kobayashi. Retrieved from https://idiyas.com/inventor/yasuo-kobayashi-pp8usyro

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5 

% Patents Active = 80.0

Average Co-Inventor Count = 1.6

ph-index = 3

Forward Citations = 56(Granted Patents)


Location History:

  • Saitama, JP (1997 - 2000)
  • Kanagawa, JP (1995 - 2013)

Company Filing History:


Years Active: 1995-2013

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5 patents (USPTO):Explore Patents

Title: Yasuo Kobayashi: Innovator in Semiconductor Technology

Introduction

Yasuo Kobayashi is a prominent inventor based in Kanagawa, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 5 patents. His work focuses on enhancing the efficiency and performance of semiconductor memory devices.

Latest Patents

One of his latest patents is for a semiconductor memory device that incorporates a new bit line hierarchization method. This innovation enables further reduction of power consumption. The device features multiple memory blocks arranged in a matrix configuration, along with main bit lines corresponding to these blocks. Each memory block consists of multiple memory cells, sub bit lines, word lines, and a switch circuit that connects a main bit line to any of the sub bit lines. This design allows for efficient reading of target cells by selecting the appropriate main bit line, sub bit line, and word line.

Another notable patent is for a static random access memory (SRAM) that includes a memory cell connected to a pair of bit lines. This SRAM is supplied with a power supply voltage from a first power supply and features a precharge circuit that precharges the bit lines with a precharge voltage. The voltage reducing circuit includes a control circuit that amplifies a difference input of a reference voltage to output a control signal, which is crucial for generating the precharge voltage.

Career Highlights

Yasuo Kobayashi has worked with several esteemed companies in the semiconductor industry, including Fuji Electric Co., Ltd. and Renesas Electronics Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas in semiconductor technology.

Collaborations

Throughout his career, Yasuo has collaborated with notable professionals in the field, including Koichi Ueki and Shigenori Kinoshita. These collaborations have contributed to the advancement of semiconductor technologies and innovations.

Conclusion

Yasuo Kobayashi is a distinguished inventor whose work in semiconductor technology has led to significant advancements in memory devices. His innovative patents reflect his commitment to improving efficiency and performance in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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