Fuji Electric Co., Ltd.

Renesas Electronics Corporation

Yasuo Kobayashi

Koichi Ueki

Shigenori Kinoshita

Kouichi Ueki

Masahiro Motonobu

A semiconductor memory device provided with a new bit line hierarchization method that enables further reduction of power consumption is provided. The semiconductor memory device includes multiple memory blocks provided in a matrix configuration and multiple main bit lines provided in correspondence with the memory blocks. Each of the memory blocks includes: multiple memory cells provided in a matrix configuration; multiple sub bit lines provided on a column-by-column basis; multiple word lines provided with respect to each of columns and rows and common to multiple memory blocks; and a switch circuit that couples a corresponding main bit line to any of the sub bit lines. In the operation of reading a target cell as the target of read, a main bit line corresponding to the target cell is selected, a sub bit line corresponding to the column of the target cell is selected through the switch circuit; and a word line corresponding to the column and the row of the target cell is selected from among the word lines.

Semiconductor memory device

A static random access memory includes: a memory cell connected with a pair of bit lines and supplied with a power supply voltage from a first power supply; a precharge circuit configured to precharge the pair of bit lines with a precharge voltage; and a voltage reducing circuit including: a control circuit comprising a differential amplifier circuit configured to amplify a difference input of a reference voltage generated through resistance division of the power supply voltage and the precharge voltage supplied to a node to output a control signal; and a voltage reduction control transistor connected between the node and the first power supply and configured to generate the precharge voltage in response to the control signal. The precharge circuit includes: precharge transistors configured to control supply of the precharge voltage to the bit lines in response to a first precharge control signal.

SRAM and method for accessing SRAM

A switch circuit comprising a semiconductor switch and an inverse-parallel diode is connected between a main electricity storage unit 4 and a primary winding 142P of an insulating transformer 142 and a switch circuit including a semiconductor switch and a diode is connected in inverse-parallel between a secondary winding 142S of the insulating transformer 142 and an auxiliary electricity storage unit 10. The switch circuits are controlled on/off, whereby power is supplied from the main electricity storage unit 4 to the auxiliary electricity storage unit 10 or from the auxiliary electricity storage unit 10 to the main electricity storage unit 4 for charging the electricity storage unit 10 or 4.

Insulation-type DC-DC power conversion unit and electric system for

A power transformer is formed of a pair of cores having wiring storage portions, at least one primary winding formed of a spirally wound flat ring having a pair of primary leading portions, at least one secondary winding formed of a flat plate, at least one spacer interposed between the flat ring and the flat plate, and an insulation member mounted in the wiring storage portions of the cores. The flat ring, flat plate and at least one spacer for insulating the flat ring and the flat plate are housed in the insulation member. The insulation member has an opening for allowing the primary leading portions to pass therethrough. In order to insulate the primary leading portions from burrs of the secondary winding, a protrusion may be formed on an outer periphery of the spacer to be located under the primary leading portions, or a cut-out portion may be formed in the flat plate.

Power transformer

In a switching power supply, electric current is supplied through a switching device to a load located away from the switching power supply. The electric current at the load is detected by a remote detecting device at remote detecting terminals. The remote detecting device includes a differential amplifier and a comparator connected to an output terminal of the differential amplifier. The comparator compares an output voltage of the differential amplifier with a reference voltage and outputs an alarm signal when the output voltage of the differential amplifier is lower than the reference voltage. A control device is connected to the switching device, the output terminal of the remote detecting device and a first reference voltage supply device. The control device changes ON-OFF duty ratio of the switching device by comparing the output voltage of the differential amplifier with the first reference voltage to control an output voltage of the switching device at a predetermined value. A first overvoltage protecting device is connected to the control device for protecting the load from overvoltage by monitoring the output of the switching device.

Growing community of inventors

Kanagawa, Japan

Yasuo Kobayashi