Yarsun Hsu is a notable inventor based in Pleasantville, NY (US). He has made significant contributions to the field of computer architecture, particularly in multi-processor environments. With a total of 9 patents to his name, Hsu's work has had a profound impact on how cache systems operate in shared memory architectures.

Latest Patents

Hsu's latest patents include a method for providing virtual atomicity in multi-processor environments with access to multilevel caches. This innovative method ensures virtual atomic invalidation in a multilevel cache system, allowing for efficient handling of invalidation signals across various cache levels. Another significant patent is the hierarchical bus simple COMA architecture for shared memory, which maintains cache coherency in shared memory multiprocessor systems. This invention introduces an additional shared owner state, enhancing the efficiency of read and write requests in complex cache systems.

Career Highlights

Yarsun Hsu is currently employed at International Business Machines Corporation (IBM), where he continues to develop cutting-edge technologies. His work at IBM has positioned him as a leader in the field of computer architecture, particularly in the realm of cache management and multi-processor systems.

Collaborations

Hsu has collaborated with several talented individuals throughout his career, including Sandra Johnson Baylor and Anthony Simon Bolmarcich. These collaborations have contributed to the advancement of technology in their respective fields.

Conclusion

Yarsun Hsu's contributions to the field of computer architecture are invaluable. His innovative patents and work at IBM demonstrate his commitment to advancing technology in multi-processor environments. Hsu's legacy as an inventor will continue to influence future developments in this critical area.

Profile summary based on public USPTO records.

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