Switch queue structure for one-network parallel processor systems

Abstract

A switch queue structure for one-network parallel processor systems minimizes chip count and reduces the possibility of deadlock which might otherwise occur with this type of switch structure. The switch queue structure comprises a plurality of input ports and a plurality of output ports equal in number to a number of processor/memory elements (PMEs) in a parallel processor system. A plurality of identical stages interconnect the plurality of input ports and the plurality of output ports. Each stage includes a plurality of first groups of first-in, first-out (FIFO) registers storing request messages, a plurality of second groups of first-in, first-out registers storing response messages, and a plurality of multiplexers. Each of the multiplexers have inputs connected to the FIFO registers in each of the first and second groups for routing responses to memory requests from addressed processor/memory elements to requesting processor/memory elements and for routing memory requests from processor/memory elements to addressed processor/memory elements.