Fremont, CA, United States of America

Yang-Chin Shih

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yang-Chin Shih. Retrieved from https://idiyas.com/inventor/yang-chin-shih

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2002

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1 patent (USPTO):Explore Patents

Title: Yang-Chin Shih and Integrated-Circuit Passivation

Introduction

Yang-Chin Shih is an inventor associated with Fremont, California, and Intel Corporation. His patent work addresses passivation for integrated circuits, with a focus on protecting closely spaced metal features and bond-pad areas. The supplied information lists 1 patent for him.

Latest Patents

Shih’s listed patent, “Passivation for Tight Metal Geometry,” describes a method for passivating an integrated circuit. The method deposits a first dielectric over the circuit’s top side, exposes part of a bond pad, and then deposits a second dielectric made from a material substantially impermeable to moisture. It subsequently exposes another portion of the bond pad within the first exposed area. This approach is intended to provide moisture protection while preserving access to the bond pad.

Career Highlights

Shih’s listed invention concerns a practical challenge in integrated-circuit fabrication: protecting device surfaces without obstructing the bond-pad area needed for electrical connections. The patent identifies Intel Corporation as his company affiliation.

Collaborations

The supplied information names Jan V. Shubert and Glen N. Wada as Shih’s coworkers. Their inclusion indicates professional connections, but the available details do not specify their roles in the patent.

Conclusion

Yang-Chin Shih’s listed patent presents a dielectric passivation method that combines moisture protection with access to an integrated-circuit bond pad.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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