Wuhan, China

Xuelian Yu

This inventor holds 1 USPTO granted patent and 1 published patent application. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Xuelian Yu. Retrieved from https://idiyas.com/inventor/xuelian-yu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Xuelian Yu and Semiconductor Innovation

Introduction

Xuelian Yu is an inventor associated with Wuhan, China. Her patent work addresses semiconductor device design and fabrication, with a focus on adapting gate-spacer thicknesses for different device types.

Latest Patents

The provided information lists one patent for Yu: Semiconductor Apparatus, Fabrication Method Thereof and Memory System. The disclosure describes using two dielectric deposition operations to form gate spacers of different thicknesses in a semiconductor apparatus. This approach can provide a relatively thick spacer for a high-voltage device and a thinner spacer for a low-voltage device, including one less than 8 nanometers thick. The patent record provided identifies 1 patent.

Career Highlights

Yu’s listed patent highlights an approach to semiconductor fabrication that accommodates the differing requirements of high- and low-voltage devices within an apparatus. The described method aims to support both thicker and thinner gate spacers through separate dielectric deposition operations.

Collaborations

The provided information names Yanwei Shi and Hu Ding as Yu’s coworkers. Their specific roles in the patent or related work are not stated.

Conclusion

Xuelian Yu’s listed patent focuses on tailoring gate-spacer thicknesses through semiconductor fabrication techniques, reflecting an effort to meet the needs of different device types within a memory system.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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