Xiaozhou Che

Title: Xiaozhou Che and Semiconductor Annealing Innovation.

Introduction

Xiaozhou Che is an inventor associated with Applied Materials, Inc., in Santa Clara, California. Her patent work addresses materials and processes for capping substrates during high-temperature annealing.

Latest Patents

Che is credited with 1 patent, titled “Interfacial Layer for Anneal Capping Layer.” The invention describes forming an interfacial layer on a substrate before depositing an amorphous carbon capping layer and annealing the substrate at approximately 1,500 degrees Celsius or higher. The interfacial layer may use amorphous silicon, amorphous silicon carbide, or amorphous silicon carbonitride, and may be approximately 5 to 100 nanometers thick. The method can be applied to planar and three-dimensional structures.

Career Highlights

Che’s patent reflects work on interface and capping-layer design for semiconductor processing. By incorporating a material related to an element of a chemical compound used in the substrate, the approach is intended to support annealing processes at very high temperatures.

Collaborations

Che’s listed coworkers include Yi Zheng and Qiang Ma. The patent is associated with Applied Materials, Inc.

Conclusion

Xiaozhou Che’s patent focuses on an interfacial-layer approach to capping substrates for high-temperature annealing, contributing to semiconductor process innovation.