Hangzhou, China

Xiao Yu

This inventor holds 4 USPTO granted patents. Top assignee: Zhejiang Lab. Active years: 2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Xiao Yu. Retrieved from https://idiyas.com/inventor/xiao-yu-1vbjc44c

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.9

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2024

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4 patents (USPTO):Explore Patents

Title: Innovations of Inventor Xiao Yu

Introduction

Xiao Yu is a prominent inventor based in Hangzhou, China. He has made significant contributions to the field of computing technology, particularly in the area of Boolean logic and circuit design. With a total of 4 patents to his name, his work is paving the way for advancements in memory computing.

Latest Patents

Xiao Yu's latest patents include a method, unit, and circuit for implementing Boolean logic based on computing-in-memory transistors. This innovative method utilizes the characteristics and read-write modes of computing-in-memory transistors. The basic unit consists of a computing-in-memory transistor and a pull resistor, which is connected in series with the transistor. The gate of the transistor operates independently, allowing the basic units to implement sixteen Boolean logic operations through various circuit structures and voltage configuration schemes. Compared to conventional CMOS transistors, this approach optimizes circuit density and computing speed by reducing data transmission between storage and processing units.

Another notable patent is the full adder circuit and multi-bit full adder. This invention discloses a full adder circuit where an in-memory computing field-effect transistor stores data and performs logic operations based on different input signals. The design achieves a low-area full adder circuit with minimal transistors, significantly reducing the area and complexity compared to traditional CMOS full adder circuits. This innovation saves 19 transistors, showcasing the efficiency of Xiao Yu's designs.

Career Highlights

Xiao Yu is currently employed at Zhejiang Lab, where he continues to develop cutting-edge technologies in the field of computing. His work is characterized by a focus on enhancing the efficiency and performance of electronic circuits.

Collaborations

Xiao Yu collaborates with talented individuals such as Jiani Gu and Songnan Ren, contributing to a dynamic research environment that fosters innovation.

Conclusion

Xiao Yu's contributions to the field of computing through his innovative patents demonstrate his commitment to advancing technology. His work not only enhances circuit design but also paves the way for future developments in memory computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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