Communication method for multi-chip neural network algorithm based on fpga main control

Abstract

A communication method for a multi-chip neural network algorithm based on a FPGA main control, which designs original data frames, status frames, layered data frames, layered weight frames, computation result frames, layered data request frames, layered weight request frames, computation result request frames and running status request frames, and then completes image processing based on the neural network algorithm according to the scheduling of transmitting and receiving processes. The present disclosure ensure that communication of multi-layer data structures and various data types based on the neural network algorithm, and accurately schedules the transmitting and receiving of data required by the main control and each chip in the multi-chip system, and sends out data request commands; it plays a very active role in receiving, transmitting and feeding back the running status of the chip and the errors and error types.