This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2013.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2013
Title: William R. Dufresne: Inventor in Circuit Verification
Introduction
William R. Dufresne is an inventor associated with North Attleborough, Massachusetts. His patent work concerns circuit-design verification, using constrained random simulation to help achieve temporal coverage goals.
Latest Patents
The provided information lists one patent for Dufresne: “Constrained Random Simulation Coverage Closure Guided by a Cover Property.” The invention describes a system that verifies a circuit design by applying random input stimuli while using a finite state automaton to monitor circuit inputs and outputs. Soft constraints associated with the automaton bias the stimuli, making it more likely that the simulation will progress through a sequence of states that satisfies a specified temporal coverage property. Dufresne is credited with 1 patent.
Career Highlights
Dufresne is associated with Synopsys, Inc., a company whose work includes electronic design automation and semiconductor design tools. His patent reflects an approach to improving simulation coverage during circuit verification.
Collaborations
The listed coworkers associated with Dufresne include Surrendra A. Dudani and Eduard Rudolf Cerny. Their names provide context for the professional network connected with his patent work.
Conclusion
William R. Dufresne’s documented invention applies constrained random simulation to guide circuit verification toward temporal coverage goals, highlighting his contribution to electronic design automation.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile