Taoyuan, Taiwan

Wen-Liang Yeh

USPTO Granted Patents = 6 

Average Co-Inventor Count = 3.8

ph-index = 1

Forward Citations = 7(Granted Patents)


Location History:

  • Hsinchu County, TW (2020)
  • Hsinchu, TW (2021)
  • Taoyuan, TW (2019 - 2022)

Company Filing History:


Years Active: 2019-2022

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6 patents (USPTO):Explore Patents

Title: Innovations of Wen-Liang Yeh

Introduction

Wen-Liang Yeh is a prominent inventor based in Taoyuan, Taiwan. He has made significant contributions to the field of chip packaging and substrate structures. With a total of 6 patents to his name, his work continues to influence advancements in technology.

Latest Patents

Wen-Liang Yeh's latest patents include a method of manufacturing a chip packaging structure. This innovative chip packaging structure features a circuit redistribution structure, a chip, a sealing layer, and an antenna pattern. The circuit redistribution structure consists of a first and a second circuit layer, along with a conductive pad. The second circuit layer is positioned on and electrically connected to the first circuit layer, while the conductive pad is electrically connected to the second circuit layer. The chip is placed on the circuit redistribution structure and is electrically connected to the second circuit layer. The sealing layer, which has an opening and a groove, covers the chip and the circuit redistribution structure, with the opening exposing the conductive pad. Additionally, a portion of the groove communicates with the opening. The antenna pattern comprises a first and a second portion, where the first portion covers the sidewalls of the opening and is electrically connected to the conductive pad, and the second portion is filled in the groove and electrically connected to the first portion.

Another notable patent is related to a substrate structure and its manufacturing method. This substrate structure includes a glass substrate, a first circuit layer, a second circuit layer, and at least one conductive region. The glass substrate has a first surface and a second surface opposing the first surface. The first circuit layer is located on the first surface, while the second circuit layer is on the second surface. The conductive region consists of multiple conductive micro vias that penetrate through the glass substrate. These conductive micro vias are electrically connected to both the first and second circuit layers, with a via size ranging from 2 µm to 10 µm.

Career Highlights

Wen-Liang Yeh is currently associated with Unimicron Technology Corporation, where he continues to innovate and develop new technologies. His work has been instrumental in enhancing the efficiency and effectiveness of chip packaging and substrate structures.

Collaborations

Wen-Liang Yeh has collaborated with several talented individuals, including Chun-Hsien Chien and Chien-Chou Chen, who have contributed to his projects and innovations.

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