The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2020
Filed:
Dec. 17, 2018
Applicant:
Unimicron Technology Corp., Taoyuan, TW;
Inventors:
Wen-Liang Yeh, Hsinchu County, TW;
Chun-Hsien Chien, New Taipei, TW;
Chien-Chou Chen, Hsinchu County, TW;
Cheng-Hui Wu, New Taipei, TW;
Assignee:
Unimicron Technology Corp., Taoyuan, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/02 (2006.01); H05K 3/10 (2006.01); H05K 3/30 (2006.01); H05K 3/46 (2006.01); H05K 3/28 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/115 (2013.01); H05K 1/0306 (2013.01); H05K 3/0094 (2013.01); H05K 3/28 (2013.01); H05K 3/3452 (2013.01); H05K 2201/2009 (2013.01);
Abstract
A carrier structure including a glass substrate, a buffer layer, and an inner circuit layer is provided. The glass substrate has a first surface, a second surface opposite to the first surface, and at least one through hole penetrating through the glass substrate. The buffer layer is disposed on the first surface and the second surface of the glass substrate. The inner circuit layer is disposed on the buffer layer and in the through hole of the glass substrate. The inner circuit layer exposes a part of the buffer layer.