Chongqing, China

Weizhong Chen

This inventor holds 1 USPTO granted patent. Top assignee: Chongqing University of Posts and Telecommunications. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Weizhong Chen. Retrieved from https://idiyas.com/inventor/weizhong-chen-wc6exuhs

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 8.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Weizhong Chen: Innovator in LDPC Decoder Systems

Introduction

Weizhong Chen is a notable inventor based in Chongqing, China. He has made significant contributions to the field of decoder hardware design, particularly through his innovative patent related to layered semi-parallel LDPC decoder systems.

Latest Patents

Weizhong Chen holds a patent for a "Layered semi-parallel LDPC decoder system having a single permutation network." This invention pertains to a layered semi-parallel LDPC decoder system that utilizes a single permutation network. The system features a layered decoding architecture, a semi-parallel decoding structure, and a pipeline design that enhances the efficiency of the decoding process. By modifying the cyclic shift value of information blocks, the invention effectively reduces the hardware resources required for the decoder while maintaining high throughput.

Career Highlights

Weizhong Chen is affiliated with the Chongqing University of Posts and Telecommunications, where he continues to advance research in decoder systems. His work has been instrumental in improving the performance and resource efficiency of decoding hardware.

Collaborations

Weizhong has collaborated with notable colleagues, including Hongsheng Zhang and Taiyun Ding, contributing to the advancement of technology in their field.

Conclusion

Weizhong Chen's innovative work in the development of LDPC decoder systems showcases his expertise and commitment to enhancing decoder hardware design. His contributions are paving the way for more efficient decoding technologies in the future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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