Layered semi parallel ldpc decoder system having single permutation network

Abstract

The present invention relates to a layered semi-parallel LDPC decoder system having a single permutation network, and belongs to the field of decoder hardware design. The system comprises a layered decoding architecture of the single permutation network, a layered semi-parallel decoding architecture of the single permutation network, a pipeline design for layered semi-parallel decoding and a hardware framework of a layered semi-parallel LDPC decoder. The present invention removes a permutation network module between a check node and a variable node by modifying the cyclic shift value of each information block transferred from the variable node to the check node, i.e., the cyclic shift operation of the decoder can be completed through the single permutation network so as to reduce hardware resources of the decoder. A semi-parallel decoding structure is adopted, and meanwhile, a pipeline is added between half layers. Compared with a decoder with a layered full-parallel structure, a decoder with a semi-parallel structure has the degree of parallelism of a variable node equal to only half of the code length but can achieve ¾ of the throughput as well as reduce hardware resources by half.