logo

For the Inventor, By the Inventor

Austin, TX, United States of America

Viresh Paruthi

USPTO Granted Patents = 110 

Average Co-Inventor Count = 3.9

ph-index = 10

Forward Citations = 469(Granted Patents)

Forward Citations (Not Self Cited) = 374(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal110 out of 164,197 
 
International Business Machines Corporation
 patents

Years Active: 2002-2025

Loading Chart...
Areas of Expertise:
Integrated Circuit Design
Formal Verification
Random Number Generators
Model Checking
Circuit Verification
Binary Decision Diagrams
State Transition Machines
Structural Satisfiability Solver
Sequential Equivalence Checking
Design Verification
Combinational Transformations
Predicate-Based Minimization
110 patents (USPTO):Explore Patents
1. 12204832 - Logical clock connection in an integrated circuit design (2025-01-21),
2. 12050852 - Signal pre-routing in an integrated circuit design (2024-07-30),
3. 11740872 - Detection of unintended dependencies in hardware designs with pseudo-random number generators (2023-08-29),
4. 11733295 - Methods and systems for identifying flaws and bugs in integrated circuits, for example, microprocessors (2023-08-22),
5. 11675009 - Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors (2023-06-13),
6. 11663381 - Clock mapping in an integrated circuit design (2023-05-30),
7. 11200361 - Scalable model checking in functional verification by integrating user-guided abstraction (2021-12-14),
8. 11150298 - Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors (2021-10-19),
9. 10970444 - Methods and systems to verify correctness of bug fixes in integrated circuits (2021-04-06),
10. 10565338 - Equivalency verification for hierarchical references (2020-02-18),
11. 9471327 - Verifying forwarding paths in pipelines (2016-10-18),
12. 9459878 - Verifying forwarding paths in pipelines (2016-10-04),
13. 9436582 - Calculating an immediate parent assertion statement for program verification (2016-09-06),
14. 9280496 - Formal verification of arbiters (2016-03-08),
15. 9063807 - Method and structure for provably fair random number generator (2015-06-23),

Title: Viresh Paruthi - Innovator from Austin, TX

Introduction: Viresh Paruthi is a renowned inventor based in Austin, Texas, known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: Viresh Paruthi holds several patents in the areas of technology, healthcare, and sustainability, showcasing his diverse range of interests and expertise.

Career Highlights: With a successful career spanning over two decades, Viresh Paruthi has worked with leading companies and research institutions, consistently pushing the boundaries of what is possible through his inventive spirit.

Collaborations: Throughout his career, Viresh Paruthi has collaborated with top universities, tech companies, and healthcare organizations, fostering a culture of innovation and driving forward progress in multiple industries.

Conclusion: Viresh Paruthi's passion for innovation and his relentless drive to create a positive impact on the world make him a truly inspiring figure in the realm of inventors and innovators.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…