The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2025
Filed:
Sep. 07, 2021
International Business Machines Corporation, Armonk, NY (US);
Ali S. El-Zein, Austin, TX (US);
Viresh Paruthi, Austin, TX (US);
Alvan Wing Ng, Austin, TX (US);
Benedikt Geukes, Stuttgart, DE;
Klaus-Dieter Schubert, Schoenaich, DE;
Robert Alan Cargnoni, Austin, TX (US);
Michael Hemsley Wood, Poughkeepsie, NY (US);
Stephen Gerard Shuma, Underhill, VT (US);
Wolfgang Roesner, Austin, TX (US);
Chung-Lung K. Shum, Wappingers Falls, NY (US);
Edward Armayor McQuade, Katonah, NY (US);
Derek E. Williams, Round Rock, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A first plurality of hardware description language (HDL) files describe a hierarchical integrated circuit design utilizing a simplified HDL syntax that omits specification of logical clock connections for at least some entities in the hierarchical integrated circuit design. The hierarchical integrated circuit design as described by the first plurality of HDL files is processed to automatically add logical clock connections for entities in the hierarchical integrated circuit design for which specification of logical clock connections are omitted in the first plurality of HDL files. Based on the processing, a second plurality of HDL files defining the hierarchical integrated circuit design is generated.