The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2021
Filed:
Dec. 11, 2020
Converting formal verification testbench drivers with nondeterministic inputs to simulation monitors
International Business Machines Corporation, Armonk, NY (US);
Bradley Donald Bingham, Austin, TX (US);
Viresh Paruthi, Austin, TX (US);
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
Techniques include configuring a sequential circuit monitor having been generated by applying a quantifier elimination to each random bit position of random inputs associated with a formal verification driver and selecting a value for random inputs to drive a next stage logic of sequential circuit simulation monitor, a state of the next stage logic being used by sequential circuit simulation monitor to generate sequential inputs to match those permitted by formal verification driver, formal verification driver being specified for a DUT input interface. An equivalence check between sequential circuit simulation monitor and original formal driver matches the same set of sequential inputs permitted original formal driver. The sequential circuit simulation monitor is coupled to a simulation environment and the DUT in simulation environment, sequential circuit simulation monitor being configured to flag an input sequence from the simulation environment not permitted by formal verification driver based on the sequential inputs.