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For the Inventor, By the Inventor

South Whitehall, PA, United States of America

Virendra V Rana

This inventor holds 8 USPTO granted patents. Top assignee: At&t Bell Laboratories. Active years: 1984-1994.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Virendra V Rana. Retrieved from https://idiyas.com/inventor/virendra-v-rana-23w95qds

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 8

% Patents Active = 100.0

Average Co-Inventor Count = 2.2

ph-index = 4

Forward Citations = 75(Granted Patents)


Location History:

  • Berkeley Heights, NJ (US) (1984 - 1985)
  • South Whitehall Township, Lehigh County, PA (US) (1991 - 1994)

Company Filing History:

goldMedal8 out of 3,345 
 
At&t Bell Laboratories
 patents

Years Active: 1984-1994

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8 patents (USPTO):Explore Patents
1. 5328872 - Method of integrated circuit manufacturing using deposited oxide (1994-07-12),
2. 5227335 - Tungsten metallization (1993-07-13),
3. 5141897 - Method of making integrated circuit interconnection (1992-08-25),
4. 5135886 - Integrated circuit fabrication utilizing amorphous layers (1992-08-04),
5. 5084415 - Metallization processing (1992-01-28),
6. 4985371 - Process for making integrated-circuit device metallization (1991-01-15),
7. 4544438 - Liquid phase epitaxial growth of bismuth-containing garnet films (1985-10-01),
8. 4468438 - Garnet epitaxial films with high Curie temperatures (1984-08-28),

Title: The Innovations of Virendra V Rana

Introduction

Virendra V Rana is a notable inventor based in South Whitehall, PA (US). He has made significant contributions to the field of integrated circuit manufacturing, holding a total of 8 patents. His work has had a profound impact on the technology industry, particularly in enhancing the quality and efficiency of semiconductor devices.

Latest Patents

Among his latest patents is a method of integrated circuit manufacturing using deposited oxide. This innovation reduces contamination of LPCVDBP TEOS films by preventing volatile compounds from reaching the deposition portion of the furnace. This process minimizes the production of chemically generated particles that can contaminate the dielectric film. Another significant patent involves tungsten metallization, where the adhesion of tungsten to an underlying dielectric layer is improved through the use of a thin glue layer of either TiN or Al.

Career Highlights

Virendra V Rana has had a distinguished career at AT&T Bell Laboratories, where he has been instrumental in advancing semiconductor technology. His expertise in integrated circuit manufacturing has positioned him as a key figure in the field, contributing to numerous innovations that enhance device performance.

Collaborations

Throughout his career, Virendra has collaborated with esteemed colleagues, including Ajit S Manocha and Lowell Henry Holschwandner. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.

Conclusion

Virendra V Rana's contributions to the field of integrated circuit manufacturing are noteworthy. His patents reflect a commitment to improving technology and enhancing the quality of semiconductor devices. His work continues to influence the industry and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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