Veera Chockalingam

Title: Veera Chockalingam: Innovator in Memory Calibration Technology

Introduction

Veera Chockalingam is a notable inventor based in Santa Clara, CA, who has made significant contributions to the field of memory calibration technology. With a total of two patents to his name, Chockalingam's work focuses on enhancing the performance and efficiency of memory subsystems.

Latest Patents

Chockalingam's latest patents include a groundbreaking invention related to memory calibration with a margin check. This innovation involves a memory subsystem that comprises a memory and a memory controller. The memory controller is equipped with a calibration circuit that performs horizontal memory calibrations during an initialization process for various performance states. It determines and stores information indicative of differences between calibration results for pairs of performance states. Furthermore, the memory controller is designed to set initial memory parameters for a second performance state based on these differences, allowing operation to commence in the new state without the need for an initial horizontal calibration.

Career Highlights

Chockalingam is currently employed at Apple Inc., where he continues to develop innovative solutions in memory technology. His work has been instrumental in advancing the capabilities of memory subsystems, contributing to the overall performance of computing devices.

Collaborations

Chockalingam has collaborated with notable colleagues, including Robert E. Jeter and Jingkui Zheng, who is a talented woman in the field. These collaborations have fostered an environment of innovation and creativity, leading to significant advancements in their respective projects.

Conclusion

Veera Chockalingam's contributions to memory calibration technology exemplify the impact of innovative thinking in the tech industry. His patents reflect a commitment to enhancing memory subsystem performance, making him a valuable asset to Apple Inc. and the broader field of technology.