Apple Inc.

Veera Chockalingam

Robert E Jeter

Naveen Kumar Korada

Jingkui Zheng

Ritesh J Shah

Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.

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Santa Clara, CA, United States of America

Veera Chockalingam