Fremont, CA, United States of America

Vasudevan Gopalakrishnan

This inventor holds 1 USPTO granted patent. Top assignee: Adesto Technologies Corporation. Active years: 2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vasudevan Gopalakrishnan. Retrieved from https://idiyas.com/inventor/vasudevan-gopalakrishnan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2014

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1 patent (USPTO):Explore Patents

Title: Innovations by Vasudevan Gopalakrishnan

Introduction

Vasudevan Gopalakrishnan is an accomplished inventor based in Fremont, CA. He has made significant contributions to the field of programmable impedance elements, particularly through his innovative patent.

Latest Patents

Gopalakrishnan holds a patent for CBRAM/ReRAM with improved program and erase algorithms. This patent outlines structures and methods for controlling the operation of a programmable impedance element. The method includes receiving a program or erase command, selecting an operation algorithm from multiple options, determining option variables for the selected algorithm, and executing the command through various program and erase operations.

Career Highlights

He is currently associated with Adesto Technologies Corporation, where he applies his expertise in developing advanced technologies. His work focuses on enhancing the efficiency and functionality of programmable impedance elements.

Collaborations

Some of his notable coworkers include Foroozan Sarah Koushan and Juan Pablo Saenz Echeverry, who contribute to the innovative environment at Adesto Technologies Corporation.

Conclusion

Vasudevan Gopalakrishnan's contributions to the field of programmable impedance elements highlight his role as a key innovator in technology. His patent reflects a commitment to advancing the capabilities of electronic components.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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