Hopewell Junction, NY, United States of America

Valerie D Lehner

This inventor holds 2 USPTO granted patents. Top assignee: International Business Machines Corporation. Active years: 2002-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Valerie D Lehner. Retrieved from https://idiyas.com/inventor/valerie-d-lehner

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 50.0

Average Co-Inventor Count = 2.4

ph-index = 1

Forward Citations = 20(Granted Patents)


Company Filing History:


Years Active: 2002-2008

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2 patents (USPTO):Explore Patents

Title: Innovations by Valerie D. Lehner

Introduction

Valerie D. Lehner is a notable inventor based in Hopewell Junction, NY (US). She has made significant contributions to the field of integrated circuit design, holding 2 patents that showcase her innovative approach to pattern matching in circuit layouts.

Latest Patents

One of her latest patents is titled "Method of matching layout shapes patterns in an integrated circuit using Walsh patterns." This method focuses on matching patterns through an orthogonal sub-space projection of layout shapes using Walsh patterns. It performs a preliminary density feature extraction of a circuit design layout, allowing users to define a pattern and conduct a high-resolution search to locate all instances of that pattern. The method generates a sorted list of layout windows, ranging from the most similar to quantitatively less similar, significantly reducing false positives compared to prior art.

Another important patent is "Pattern-matching for transistor level netlists." This single pattern-matching algorithm allows for both exact and inexact pattern matching, enabling transistor-level design automation tools to perform various analyses prior to manufacturing custom logic. Circuit designers can specify which pattern external nets may be matched inexactly, while the remaining connections are matched using exact isomorphism constraints. This method reduces the number of patterns that circuit designers must generate and eliminates the need for an exponential number of patterns by providing an inexact pattern matcher.

Career Highlights

Valerie D. Lehner is currently employed at the International Business Machines Corporation (IBM), where she continues to innovate in the field of circuit design. Her work has had a significant impact on the efficiency and accuracy of circuit design processes.

Collaborations

Throughout her career, Valerie has collaborated with esteemed colleagues such as John Maxwell Cohn and Ulrich Alfons Finkler. These collaborations have further enriched her contributions to the field.

Conclusion

Valerie D. Lehner's innovative patents and contributions to integrated circuit design highlight her expertise and dedication to advancing technology. Her work continues to influence the industry and inspire future innovations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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