The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7472364 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 30, 2008

Filed:

Aug. 02, 2006
Applicants:

Valerie D. Lehner, Hopewell Junction, NY (US);

Timothy S. Lehner, Hopewell Junction, NY (US);

Inventors:

Valerie D. Lehner, Hopewell Junction, NY (US);

Timothy S. Lehner, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for matching patterns, based on an orthogonal sub-space projection of layout shapes using Walsh patterns, performs a preliminary density feature extraction of a circuit design layout, allows a user to define a pattern, and performs a high resolution search of the layout to locate all instances of the pattern. A sorted list of layout windows ranging from the most similar to quantitatively less similar is generated. The method for matching patterns significantly reduces false positives in comparison with the prior art and enables the same density data to be reused as a window is stepped in small increments across the layout.


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Lehner, Valerie. (2008). Method of matching layout shapes patterns in an integrated circuit using walsh patterns (U.S. Patent No. 7472364). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7472364

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