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For the Inventor, By the Inventor

Scarborough, Canada

Valavan Manohararajah

This inventor holds 47 USPTO granted patents and 3 published patent applications and 4 EPO patents, primarily in Integrated Circuit Design. Top assignees: Altera Corporation, Other. Active years: 2007-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Valavan Manohararajah. Retrieved from https://idiyas.com/inventor/valavan-manohararajah

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 47 

% Patents Active = 70.2

 

Average Co-Inventor Count = 2.7

ph-index = 9

Forward Citations = 285(Granted Patents)


Location History:

  • Scarbough, CA (US) (2014)
  • Scarborough, CA (US) (2015)
  • Scarbough, CA (2009 - 2017)
  • Scarborough, CA (2007 - 2020)

Company Filing History:

goldMedal46 out of 4,331 
 
Altera Corporation
 patents
silverMedal1 out of 834,453 
Other
 patents

Years Active: 2007-2020

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Areas of Expertise:
Memory Interface Calibration
Programmable Device Configuration
Physical Synthesis
Heterogeneous Programmable Device
Integrated Circuit Design
Logic Functions Mapping
Register Retiming
Pipelined Routing
Asynchronous Reset Removal
Multithreading Specification
Post-Placement Optimization
Logic Regions
47 patents (USPTO):Explore Patents
1. 10832787 - Methods for memory interface calibration (2020-11-10),
2. 10572224 - Methods and apparatus for sequencing multiply-accumulate operations (2020-02-25),
3. 10452392 - Configuring programmable integrated circuit device resources as processors (2019-10-22),
4. 10332612 - Methods for memory interface calibration (2019-06-25),
5. 10037396 - Integrated circuit device configuration methods adapted to account for retiming (2018-07-31),
6. 10019234 - Methods and apparatus for sequencing multiply-accumulate operations (2018-07-10),
7. 9911506 - Methods for memory interface calibration (2018-03-06),
8. 9891904 - Method and apparatus for optimizing implementation of a soft processor executing a fixed program on a target device (2018-02-13),
9. 9660650 - Integrated circuits with improved register circuitry (2017-05-23),
10. 9589090 - Method and apparatus for performing multiple stage physical synthesis (2017-03-07),
11. 9558849 - Methods for memory interface calibration (2017-01-31),
12. 9553590 - Configuring programmable integrated circuit device resources as processing elements (2017-01-24),
13. 9401718 - Heterogeneous programmable device and configuration software adapted therefor (2016-07-26),
14. 9360884 - Clocking for pipelined routing (2016-06-07),
15. 9245085 - Integrated circuit device configuration methods adapted to account for retiming (2016-01-26),

Title: The Innovative Journey of Valavan Manohararajah

Introduction: Valavan Manohararajah, a talented inventor hailing from Scarborough, CA, has made significant contributions to the field of innovations with his groundbreaking ideas and inventions.

Latest Patents: Valavan Manohararajah holds several patents in various technological domains, showcasing his versatility and creativity in inventing new solutions to complex problems.

Career Highlights: Throughout his illustrious career, Valavan Manohararajah has been recognized for his exceptional problem-solving skills and innovative thinking. His inventions have not only revolutionized industries but have also improved the quality of life for many individuals.

Collaborations: Valavan Manohararajah has collaborated with leading research institutions, universities, and companies to further develop and implement his inventions. His collaborative efforts have led to the successful commercialization of several groundbreaking technologies.

Conclusion: In conclusion, Valavan Manohararajah stands as a beacon of innovation in the field of inventions. His dedication to pushing the boundaries of what is possible has cemented his legacy as a pioneering inventor in Scarborough, CA.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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