The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Oct. 29, 2012
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Valavan Manohararajah, Scarborough, CA;

David Lewis, Toronto, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/173 (2006.01); G06F 9/30 (2006.01); G06F 7/57 (2006.01); G06F 7/38 (2006.01); G06F 17/30 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17708 (2013.01); G06F 9/30 (2013.01); H03K 19/1737 (2013.01); G06F 17/30221 (2013.01); G06F 17/5054 (2013.01); H03K 19/17728 (2013.01); H03K 19/17736 (2013.01);
Abstract

A programmable integrated circuit device includes a plurality of clusters of programmable logic resources. Programmable device interconnect resources allow user-defined interconnection between the clusters of programmable logic resources. A plurality of specialized processing blocks have dedicated arithmetic operators and programmable internal interconnect resources, and having inputs and outputs programmably connectable to the programmable device interconnect resources. A plurality of dedicated memory modules have inputs and outputs programmably connectable to the programmable device interconnect resources. Programmably connectable direct interconnect between at least one respective individual one of the specialized processing blocks and at least one respective individual one of the dedicated memory modules allow the formation of a processor element from a specialized processing block and a memory module. The specialized processing block may be designed with a datapath and operators arranged to support the configuring of a processor element.


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