Milpitas, CA, United States of America

Trang Pham

This inventor holds 1 USPTO granted patent. Top assignee: Infineon Technologies Ag. Active years: 2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Trang Pham. Retrieved from https://idiyas.com/inventor/trang-pham

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 23(Granted Patents)


Company Filing History:


Years Active: 2005

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Trang Pham and the 7-Track Standard Cell Library.

Introduction

Trang Pham is an inventor associated with Milpitas, California, and Infineon Technologies AG. Her patent work includes a standard-cell layout architecture designed for advanced fabrication technologies.

Latest Patents

Pham is credited with 1 patent, titled “7-tracks standard cell library.” The invention describes a seven-track standard-cell layout for fabrication technologies with design rules of 0.12 microns or smaller. It uses horizontal and vertical routing-grid spacings of 0.4 microns, producing a cell height of 2.8 microns. Power rails use M1 structures, and the cell height is divided into four tracks on the P-side and three on the N-side. For complex cells, an internal connection line made with the third metal layer (M3) is placed on a predetermined track to support the seven-track layout.

Career Highlights

The patent reflects Pham’s contribution to standard-cell architecture and integrated-circuit layout design. The disclosed approach specifies cell dimensions, routing-grid spacing, power-rail implementation, and an M3 connection structure.

Collaborations

Pham’s listed coworkers include Helena H. Nguyen and Tam Dinh Thanh Nguyen. The available information identifies her association with Infineon Technologies AG but does not specify the coworkers’ roles in the patent.

Conclusion

Trang Pham’s patent documents a detailed seven-track standard-cell architecture intended to support compact layouts for advanced semiconductor fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…