Toshihiko Hirose

This inventor holds 14 USPTO granted patents, primarily in Semiconductor Memory. Top assignee: Mitsubishi Denki Kabushiki Kaisha. Active years: 1990-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Toshihiko Hirose. Retrieved from https://idiyas.com/inventor/toshihiko-hirose

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 14

% Patents Active = 100.0

Average Co-Inventor Count = 3.9

ph-index = 9

Forward Citations = 174(Granted Patents)

Location History:

Hyogo-ken, JP (1996 - 1997)
Tokyo, JP (1998)
Hyogo, JP (1990 - 2001)

Company Filing History:

14 out of 21,351

Mitsubishi Denki Kabushiki Kaisha

patents

Years Active: 1990-2001

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Areas of Expertise:

Thin Film Transistor

Power Consumption

Semiconductor Device

Static Random Access Memory

Wiring Architecture

Memory Device

Accurate Data Writing

CMOS Output Circuit

Single Bit Line Configuration

Non-Selecting Level Generation

Circuitry Enhancements

14 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6218724 - Thin film transistor used in semiconductor memory for achieving reduction in power consumption (2001-04-17),

2. 5808930 - Semiconductor memory device having improved wiring architecture (1998-09-15),

3. 5726945 - Semiconductor device with reduced power consumption and thin film (1998-03-10),

4. 5694354 - Static random access memory device having a single bit line configuration (1997-12-02),

5. 5659513 - Static semiconductor memory device having improved characteristics (1997-08-19),

6. 5629900 - Semiconductor memory device operable to write data accurately at high (1997-05-13),

7. 5572469 - Static random access memory device having a single bit line configuration (1996-11-05),

8. 5544105 - Static semiconductor memory device having circuitry for lowering (1996-08-06),

9. 5515326 - Static semiconductor memory device having circuitry for lowering (1996-05-07),

10. 5506805 - Static semiconductor memory device having circuitry for enlarging write (1996-04-09),

11. 5491655 - Semiconductor memory device having non-selecting level generation (1996-02-13),

12. 5475638 - Static random access memory device having a single bit line configuration (1995-12-12),

13. 4988888 - CMOS output circuit with intermediate potential setting means (1991-01-29),

14. 4896299 - Static semiconductor memory device having function of resetting stored (1990-01-23),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]