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For the Inventor, By the Inventor

Hachioji, Japan

Toru Shonai

USPTO Granted Patents = 12

Average Co-Inventor Count = 5.5

ph-index = 9

Forward Citations = 436(Granted Patents)


Location History:

  • Kodaira, JP (1996 - 2007)
  • Hachioji, JP (2003 - 2007)

Company Filing History:

goldMedal12 out of 42,485 
 
Hitachi, Ltd.
 patents

Years Active: 1996-2007

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12 patents (USPTO):Explore Patents
1. 7281249 - Computer forming logical partitions (2007-10-09),
2. 7206818 - Shared memory multiprocessor system (2007-04-17),
3. 7062559 - Computer resource allocating method (2006-06-13),
4. 6874053 - Shared memory multiprocessor performing cache coherence control and node controller therefor (2005-03-29),
5. 6789173 - Node controller for performing cache coherence control and memory-shared multiprocessor system (2004-09-07),
6. 6636926 - Shared memory multiprocessor performing cache coherence control and node controller therefor (2003-10-21),
7. 6591325 - Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer (2003-07-08),
8. 6546471 - Shared memory multiprocessor performing cache coherency (2003-04-08),
9. 6516391 - Multiprocessor system and methods for transmitting memory access transactions for the same (2003-02-04),
10. 6438653 - Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system (2002-08-20),
11. 6088770 - Shared memory multiprocessor performing cache coherency (2000-07-11),
12. 5504690 - Automatic logic designing method and system (1996-04-02),

Title: The Innovations of Toru Shonai

Introduction

Toru Shonai is a prominent inventor based in Hachioji, Japan. He has made significant contributions to the field of computer technology, holding a total of 12 patents. His work focuses on enhancing the efficiency and performance of computer systems.

Latest Patents

One of Shonai's latest patents is related to a computer forming logical partitions. This invention allows a computer to control I/O allocation for partitions independently of CPU allocation. It features a scheduling means that controls allocation for partitions of the I/O adapter by time sharing, as well as a means to allocate the I/O adapter to partitions by space sharing. Additionally, it includes a mechanism to dynamically change the allocation made by a partition-control program. The computer also monitors input/output performance of each partition and maintains the Service Level Agreement (SLA) of a user program according to the performance of each partition.

Another notable patent is for a shared memory multiprocessor system. This system includes a translation lookaside buffer (TLB) in each processor and a structure designed to avoid TLB purge overhead. Each processor node is equipped with a partial main memory and a physical page map table (PPT) that stores the mapping between the physical page number of main memory and the virtual page number. The system allows for efficient memory access transactions while minimizing errors.

Career Highlights

Toru Shonai is currently employed at Hitachi, Ltd., where he continues to innovate and develop advanced technologies. His work has significantly impacted the efficiency of computer systems and has contributed to the advancement of multiprocessor systems.

Collaborations

Shonai has collaborated with notable colleagues, including Hideya Akashi and Naoki Hamanaka. Their combined expertise has fostered a productive environment for innovation and development.

Conclusion

Toru Shonai's contributions to computer technology through his patents and work at Hitachi, Ltd. highlight his role as a leading inventor in the field. His innovative solutions continue to shape the future of computing.

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