The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Aug. 04, 2003
Toshio Okochi, Union Lane, GB;
Toru Shonai, Kodaira, JP;
Naoki Hamanaka, Tokyo, JP;
Naohiko Irie, Santa Clara, CA (US);
Hideya Akashi, Kunitachi, JP;
Toshio Okochi, Union Lane, GB;
Toru Shonai, Kodaira, JP;
Naoki Hamanaka, Tokyo, JP;
Naohiko Irie, Santa Clara, CA (US);
Hideya Akashi, Kunitachi, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Multiprocessor system, having a translation lookaside buffer (TLB) in each processor, and having a structure for avoiding TLB purge overhead. Each processor node is provided with a partial main memory and a physical page map table (PPT). The PPT stores mapping between physical page number of main memory and virtual page number. Every memory access transaction for other node specifies physical address and virtual page number. Instead of strictly maintaining TLB coherency by broadcasting TLB purge transaction, an access destination node checks the coincidence between the virtual page number specified in the memory access transaction and the virtual page number mapped in the PPT when the transaction is received. If both are coincident, the memory access is executed. If not coincident, an error message is transferred to an access requesting source.