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For the Inventor, By the Inventor

Omihachiman, Japan

Toru Asano

USPTO Granted Patents = 10

Average Co-Inventor Count = 3.9

ph-index = 4

Forward Citations = 35(Granted Patents)


Location History:

  • Omihachiman, JP (2005 - 2008)
  • Austin, TX (US) (2004 - 2010)

Company Filing History:

goldMedal9 out of 164,135 
 
International Business Machines Corporation
 patents
silverMedal2 out of 52,722 
 
Kabushiki Kaisha Toshiba
 patents
bronzeMedal1 out of 832,718 
Other
 patents
where one patent can have more than one assignee

Years Active: 2004-2010

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10 patents (USPTO):Explore Patents
1. 7860172 - Self clock generation structure for low power local clock buffering decoder (2010-12-28),
2. 7423921 - Method and apparatus for wordline redundancy control of memory in an information handling system (2008-09-09),
3. 7139215 - Apparatus and method of word line decoding for deep pipelined memory (2006-11-21),
4. 7053668 - SOI sense amplifier with cross-coupled body terminal (2006-05-30),
5. 7046045 - SOI sense amplifier with cross-coupled bit line structure (2006-05-16),
6. 6944088 - Apparatus and method for generating memory access signals, and memory accessed using said signals (2005-09-13),
7. 6898135 - Latch type sense amplifier method and apparatus (2005-05-24),
8. 6885596 - Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM (2005-04-26),
9. 6850456 - Subarray control and subarray cell access in a memory module (2005-02-01),
10. 6833736 - Pulse generating circuit (2004-12-21),
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