San Jose, CA, United States of America

Tien-Chien Lee

This inventor holds 1 USPTO granted patent. Top assignee: Atrenta, Inc.. Active years: 2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tien-Chien Lee. Retrieved from https://idiyas.com/inventor/tien-chien-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2014

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1 patent (USPTO):Explore Patents

Title: Tien-Chien Lee: Innovator in Integrated Circuit Design

Introduction

Tien-Chien Lee is a notable inventor based in San Jose, CA. He has made significant contributions to the field of integrated circuit design. His innovative approach focuses on enhancing the efficiency of multiplexers in circuit design.

Latest Patents

Tien-Chien Lee holds a patent for a "System and method for large multiplexer identification and creation in a design of an integrated circuit." This patent addresses the challenges faced during the design of integrated circuits, particularly in converting functional descriptions into multiplexers. By combining multiple multiplexers into a larger one, potential design problems can be identified early, preventing costly routing congestion issues later on. The patent emphasizes the importance of detecting multiplexing functionalities and merging them when possible to achieve a more efficient implementation.

Career Highlights

Tien-Chien Lee is currently employed at Atrenta, Inc., where he continues to work on innovative solutions in integrated circuit design. His expertise in the field has led to advancements that benefit the industry as a whole.

Collaborations

He collaborates with talented coworkers such as Saurabh Verma and Satrajit Pal, contributing to a dynamic work environment that fosters innovation.

Conclusion

Tien-Chien Lee's work in integrated circuit design exemplifies the impact of innovation on technology. His patent and career achievements highlight his commitment to improving efficiency in circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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