Shenzhen, China

Tiejun Liu

This inventor holds 1 USPTO granted patent. Top assignee: Future Wei Technologies, Inc.. Active years: 2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tiejun Liu. Retrieved from https://idiyas.com/inventor/tiejun-liu-plqxfddm

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2021

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1 patent (USPTO):Explore Patents

Title: Tiejun Liu: Innovator in Integrated Circuit Packaging

Introduction

Tiejun Liu is a prominent inventor based in Shenzhen, China. He has made significant contributions to the field of integrated circuit packaging. His innovative work focuses on enhancing the performance and reliability of electronic devices.

Latest Patents

Tiejun Liu holds a patent for a technology titled "Wrapped signal shielding in a wafer fanout package." This patent presents techniques and structures aimed at improving the shielding of integrated circuit packages. The design includes a die with multiple bump sites connected to a substrate. The substrate features layers that implement signal traces and shield traces, with each shield trace linked to a ground plane through slot vias. This innovation is crucial for advancing the efficiency of electronic components.

Career Highlights

Tiejun Liu is currently employed at Future Wei Technologies, Inc., where he continues to develop cutting-edge technologies in the field of electronics. His work has garnered attention for its potential to enhance the functionality of integrated circuits.

Collaborations

Some of Tiejun Liu's notable coworkers include Shiqun Gu and Zhao Chen. Their collaborative efforts contribute to the innovative environment at Future Wei Technologies, Inc.

Conclusion

Tiejun Liu's contributions to integrated circuit packaging exemplify the importance of innovation in technology. His patent on signal shielding demonstrates a commitment to improving electronic device performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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