The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 24, 2021
Filed:
Jan. 22, 2018
Applicant:
Futurewei Technologies, Inc., Plano, TX (US);
Inventors:
Assignee:
Futurewei Technologies, Inc., Plano, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/49827 (2013.01); H01L 23/5226 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/18 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/3025 (2013.01);
Abstract
Techniques and structures for improving shielding of an integrated circuit package are provided. The integrated circuit package includes a die including a plurality of bump sites and a substrate connected to the die at the plurality of bump sites. The substrate includes at least one layer that implements one or more signal traces and a plurality of shield traces. Each shield trace in the plurality of shield traces is coupled to a ground plane by a plurality of slot vias.