Allentown, PA, United States of America

Thomas N Fogarty

This inventor holds 1 USPTO granted patent. Top assignee: Bell Telephone Laboratories. Active years: 1980.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thomas N Fogarty. Retrieved from https://idiyas.com/inventor/thomas-n-fogarty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 16(Granted Patents)


Company Filing History:


Years Active: 1980

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1 patent (USPTO):Explore Patents

Title: Thomas N. Fogarty and Patterned Silicon Nitride Layers

Introduction

Thomas N. Fogarty is an inventor associated with Allentown, Pennsylvania, and Bell Telephone Laboratories. His patent work addresses the fabrication of patterned insulating layers for integrated circuits.

Latest Patents

The supplied information lists one patent for Fogarty: “Fabrication of Patterned Silicon Nitride Insulating Layers Having Gently Sloped Sidewalls.” The patent describes forming an insulating layer, such as silicon nitride, through reactive plasma deposition while gradually lowering the substrate temperature. This temperature change affects the layer’s etching characteristics, allowing selective plasma etching to create openings with sloped sidewalls, even when the layer is overetched. The listed total is 1 patent.

Career Highlights

Fogarty’s listed work at Bell Telephone Laboratories connects his invention to integrated-circuit fabrication. The patent focuses on controlling the shape of etched openings in insulating layers, a feature relevant to the formation of circuit structures.

Collaborations

The supplied information identifies William R. Harshbarger and Roy A. Porter as Fogarty’s coworkers. Their names provide context for his professional environment at Bell Telephone Laboratories, though no specific collaboration on this patent is stated.

Conclusion

Thomas N. Fogarty’s listed patent presents a method for producing gently sloped openings in patterned silicon nitride layers, contributing to techniques for integrated-circuit fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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