Rancho Murieta, CA, United States of America

Thomas J Shewchuk

This inventor holds 2 USPTO granted patents. Top assignee: Intel Corporation. Active years: 1998-2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thomas J Shewchuk. Retrieved from https://idiyas.com/inventor/thomas-j-shewchuk

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.9

ph-index = 2

Forward Citations = 53(Granted Patents)


Company Filing History:


Years Active: 1998-2003

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2 patents (USPTO):Explore Patents

Title: The Innovative Mind of Thomas J Shewchuk

Introduction

Thomas J Shewchuk, an inventive engineer based in Rancho Murieta, California, is known for his significant contributions to the field of electronics. With a prolific record of two patents, he has demonstrated his commitment to advancing technology. His work at Intel Corporation has showcased his talent in creating innovative solutions that address complex challenges in integrated circuits.

Latest Patents

Thomas J Shewchuk's latest patented innovations include:

1. **Built-in self-testing for embedded memory** - This patent introduces an integrated circuit with a central built-in self-test unit (BIST) that utilizes internal scan chains for testing embedded memory modules. The design allows embedded memory modules to receive address and data signals from a set of input flip-flops configured as a scan chain. The BIST is adept at coupling with an input scan chain and features a pattern generator that shifts a test pattern into the input scan chain for effective testing. Moreover, the BIST incorporates address control logic to facilitate memory testing by bypassing the conventional addressing logic during operation.

2. **Five volt safe output buffer circuit** - This invention provides an input/output buffer for computer circuitry, employing a P-type transistor device that responds to data signals for controlling voltage from a primary source at the buffer input/output terminal. Additionally, it includes a first predriver circuit that delivers data signals to the P-type transistor while slowing the signal application when the terminal is at a high level. The circuit features an N-type transistor device that responds for sharing voltage from a second source at the buffer output terminal, complemented by a second predriver circuit that enhances the operation of the N-type device.

Career Highlights

Thomas J Shewchuk has made notable advancements in his career at Intel Corporation, a company recognized as a leader in semiconductor manufacturing and technology innovation. His work emphasizes improving the efficiency and reliability of embedded memory systems, contributing to Intel's reputation for high-performance computing solutions.

Collaborations

Throughout his career, Thomas has worked alongside esteemed colleagues, including Anthony Babella and Patrick P Chan. These collaborations have fostered an environment of shared knowledge and expertise, enabling the team to pioneer advancements in their respective fields.

Conclusion

Thomas J Shewchuk continues to make impactful contributions to the technology sector through his innovative patents and collaborative work at Intel Corporation. His focus on enhancing embedded memory testing and output circuitry underscores his dedication to driving progress in electronics and integrated circuits. As innovations in technology continue to evolve, inventors like Thomas pave the way for future developments.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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