Fremont, CA, United States of America

Thomas Henry Templeton, Jr


Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: Thomas Henry Templeton, Jr. - Innovator in Semiconductor Technology

Introduction

Thomas Henry Templeton, Jr. is a notable inventor based in Fremont, CA (US). He has made significant contributions to the field of semiconductor technology, particularly in the area of die attach materials and structures. His innovative approach has led to the development of a unique patent that addresses critical challenges in semiconductor packaging.

Latest Patents

Templeton holds a patent for a "System and method of reducing die attach stress and strain." This invention presents a mounting structure for a semiconductor die that effectively reduces die attach strain within the die attach material. The design maintains the electrical and thermal characteristics of the package, ensuring optimal performance. The patent outlines a structure that includes a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask creates a solder pattern that covers portions of the die attach metallization layer, allowing for multiple exposed areas that enhance the mounting surface for the semiconductor die.

Career Highlights

Throughout his career, Templeton has been associated with Power-One Limited, where he has applied his expertise in semiconductor technology. His work has focused on improving the reliability and efficiency of semiconductor devices, making significant strides in the industry.

Collaborations

Templeton has collaborated with notable colleagues, including John Alan Maxwell and Mysore Purushotham Divakar. These partnerships have fostered innovation and contributed to advancements in semiconductor technology.

Conclusion

Thomas Henry Templeton, Jr. is a distinguished inventor whose work in semiconductor technology has led to valuable innovations. His patent for reducing die attach stress and strain exemplifies his commitment to enhancing the performance of semiconductor devices.

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