The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2005

Filed:

Apr. 24, 2003
Applicants:

John Alan Maxwell, Newbury Park, CA (US);

Mysore Purushotham Divakar, San Diego, CA (US);

Thomas Henry Templeton, Jr., Fremont, CA (US);

Inventors:

John Alan Maxwell, Newbury Park, CA (US);

Mysore Purushotham Divakar, San Diego, CA (US);

Thomas Henry Templeton, Jr., Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L023/48 ;
U.S. Cl.
CPC ...
Abstract

A mounting structure for a semiconductor die that reduces die attach strain within the die attach material without sacrificing the electrical and thermal characteristics of the package. In one embodiment, the mounting structure comprises a die attach metallization layer, a solder mask, and a layer of die attach material. The solder mask forms a solder pattern over the top surface of the die attach metallization layer. The solder pattern covers a portion of the die attach metallization layer to create multiple exposed areas of the die attach metallization layer. Each exposed area is separated by the solder mask and is located under the semiconductor die when the semiconductor die is secured to the mounting structure. A layer of die attach material covers the solder pattern and fills in each one of the exposed areas to form a semiconductor die mounting surface. In another embodiment, the die attach metallization layer is divided into multiple, spaced-apart die attach pads that are electrically coupled together. A layer of die attach material covers a portion of each die attach pad and fills in the space between each die attach pad to form a semiconductor die mounting surface. A method of manufacturing the mounting structure is also disclosed.


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