This inventor holds 2 USPTO granted patents. Top assignee: Sharp Kabushiki Kaisha Corporation. Active years: 2002-2003.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Location History:
- Kashiwa, JP (2002)
- Yokohama, JP (2003)
Company Filing History:
Years Active: 2002-2003
Title: Tetsu Miyoshi: Innovator in Semiconductor Technology
Introduction
Tetsu Miyoshi is a prominent inventor based in Yokohama, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 2 patents. His work focuses on innovative methods for producing semiconductor storage devices and ferroelectric gate field-effect transistors.
Latest Patents
Miyoshi's latest patents include a semiconductor storage device and a method of producing the same. This invention involves forming a contact plug electrically connected with a MOS transistor in a first interlayer dielectric. A barrier metal material is then deposited and patterned to create an electrical connection with the contact plug. Following this, a SiN film is formed as an anti-oxygen-permeation film, which is then abraded using a chemical mechanical polishing technique to expose the top surface of the barrier metal. The process continues with the deposition of a lower electrode material, dielectric material, and upper electrode material, ensuring that the lower electrode covers the entire upper surface of the barrier metal. A second interlayer dielectric is deposited, followed by heat treatment in an oxygen ambient to recover the film quality of the capacitor dielectric.
Another notable patent is for a ferroelectric gate field-effect transistor (FET). In this invention, a dummy gate electrode is formed above the channel formation region of a semiconductor substrate. A dopant is ion-implanted into the substrate surface using the dummy gate electrode as a mask, forming a source/drain region in self-alignment. A first interlayer insulator is formed on the substrate and dummy gate electrode, which is then planarized to expose the top surface of the dummy gate. A trench is created by removing the dummy gate electrode, and a gate is formed in the trench by sequentially adding a buffer dielectric film, a ferroelectric film, and a gate electrode material. This method ensures that there is no damage to the peripheral portions of the trench and maintains the vertical components of spontaneous polarization in the ferroelectric film.
Career Highlights
Miyoshi is currently employed at Sharp Kabushiki Kaisha Corporation, where he continues to innovate in semiconductor technology. His work has been instrumental in advancing the capabilities of semiconductor devices, particularly in enhancing their performance and reliability.
Collaborations
Miyoshi has collaborated with notable colleagues such as Kazuya Ishihara and
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
