Kanagawa, Japan

Teru Yoneyama

This inventor holds 5 USPTO granted patents and 1 published patent application. Top assignees: Nec Electronics Corporation, Renesas Electronics Corporation. Active years: 2008-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Teru Yoneyama. Retrieved from https://idiyas.com/inventor/teru-yoneyama

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5 

% Patents Active = 60.0

Average Co-Inventor Count = 1.4

ph-index = 3

Forward Citations = 75(Granted Patents)


Location History:

  • Kawasaki, JP (2008 - 2009)
  • Kanagawa, JP (2009 - 2013)

Company Filing History:


Years Active: 2008-2013

Loading Chart...
5 patents (USPTO):Explore Patents

Title: Teru Yoneyama: Innovator in Display Technology

Introduction

Teru Yoneyama is a notable inventor based in Kanagawa, Japan. He has made significant contributions to the field of display technology, holding a total of 5 patents. His work focuses on enhancing the functionality and efficiency of display apparatuses and their associated driving circuits.

Latest Patents

Yoneyama's latest patents include a display apparatus and a driving circuit designed for improved output signals. One of his innovations involves a drive circuit that outputs a gradation current to an output terminal. This circuit features a drive transistor, a single differential amplifier, a resistance element, and multiple switches. The switches are controlled to output a precharge voltage during a first period while blocking the output from the drive transistor, followed by a gradation current output in a second period.

Another significant patent is a display data receiving circuit that includes a phase-locked loop (PLL) circuit. This circuit generates an internal clock signal that is an integral multiple of the frequency of differential clock signals. It also features a serial/parallel conversion circuit that can execute either single edge or double edge operations for receiving serial data signals. The PLL circuit is designed to change the frequency of the internal clock signal, enhancing the adaptability of the display system.

Career Highlights

Throughout his career, Teru Yoneyama has worked with prominent companies in the electronics sector. He has been associated with NEC Electronics Corporation and Renesas Electronics Corporation, where he contributed to various innovative projects in display technology.

Collaborations

Yoneyama has collaborated with notable colleagues in his field, including Yoshiharu Hashimoto and Yutaka Saeki. Their combined expertise has likely contributed to the advancements in the technologies they have developed together.

Conclusion

Teru Yoneyama's contributions to display technology through his patents and collaborations highlight his role as an influential inventor in the industry. His innovative designs continue to impact the way display systems operate, showcasing the importance of his work in modern technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…