The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2012
Filed:
Jul. 03, 2007
Teru Yoneyama, Kanagawa, JP;
Teru Yoneyama, Kanagawa, JP;
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Abstract
A display data receiving circuit of the present invention includes a PLL circuitwhich generates internal clock signal ICLK having an integral multiple of the frequency of differential clock signals CLK and /CLK in response to differential clock signals CLK and /CLK, and a serial/parallel conversion circuitwhich receives serial data signal transmitting display data in synchronization with the internal clock signal ICLK, and generates parallel data signal by executing serial/parallel conversion for the serial data signal. The serial/parallel conversion circuitis configured to be able to execute either a single edge operation, which receives serial data signals in response to one of a rising edge and a falling edge of the internal clock signal ICLK, or a double edge operation, which receives serial data signals in response to both of a rising edge and a falling edge of the internal clock signal ICLK. Further, the PLL circuitis configured to be able to change the frequency of the internal clock signal ICLK.