Kanagawa, Japan

Tatsumasa Hiratsuka

This inventor holds 2 USPTO granted patents and 6 published patent applications. Top assignee: Sony Semiconductor Solutions Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tatsumasa Hiratsuka. Retrieved from https://idiyas.com/inventor/tatsumasa-hiratsuka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Tatsumasa Hiratsuka: Advancing Solid-State Imaging Technology

Introduction

Tatsumasa Hiratsuka is an inventor based in Kanagawa, Japan, whose patent work focuses on solid-state imaging devices and their manufacturing. His inventions address image-sensor reliability, device structure, and the mechanical stresses that can arise during fabrication. He is associated with Sony Semiconductor Solutions Corporation and has 2 patents.

Latest Patents

Hiratsuka’s recent patent work includes two inventions related to solid-state imaging.

- **Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic device.** This invention describes a multilayer structure designed to improve the quality and reliability of a solid-state imaging device. It includes a first substrate, a differently sized second substrate directly bonded to the first, and a third substrate separated from the first by an insulating layer. A well is formed on the light-incident side of the third substrate.

- **Solid-state imaging device, manufacturing method of solid-state imaging device, and electronic apparatus.** This invention aims to reduce tensile stress between a covering film and a semiconductor element joined to a solid-state imaging element. Its structure includes a covering film that extends over an uncovered region of the imaging element and around the semiconductor element’s peripheral side surface, while leaving a clearance beside that surface. The design can reduce stress near chip edges and allow transistors to be placed closer to them.

Career Highlights

Hiratsuka’s patent portfolio reflects work on the design and manufacture of semiconductor-based imaging systems. His inventions address both the layered construction of imaging devices and the interaction between covering films and semiconductor elements, with the goal of supporting reliable device performance and practical chip layouts.

Collaborations

Hiratsuka is associated with Sony Semiconductor Solutions Corporation. His listed coworkers include Kentaro Akiyama and Takahiro Kamei.

Conclusion

Tatsumasa Hiratsuka’s patented work focuses on improving the reliability and manufacturability of solid-state imaging devices through substrate design and stress-reducing structures.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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