The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2026
Filed:
Mar. 16, 2022
Sony Semiconductor Solutions Corporation, Kanagawa, JP;
Tatsumasa Hiratsuka, Kanagawa, JP;
SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa, JP;
Abstract
An object is to provide a solid-state imaging device, a manufacturing method of a solid-state imaging device, and an electronic apparatus that are capable of reducing tensile stress produced between a covering film and a semiconductor element which is joined to a solid-state imaging element and which is covered with the covering film, and that allow transistors to be provided near chip ends. There is provided a configuration including a solid-state imaging element, a semiconductor element laminated on the solid-state imaging element and electrically connected to the solid-state imaging element, and a covering film that covers a non-lamination portion that is a region where the semiconductor element is not laminated, in a laminated surface of the solid-state imaging element where the semiconductor element is laminated, and further covers a peripheral side surface of the semiconductor element and forms a clearance between the peripheral side surface of the semiconductor element and the covering film. This configuration can reduce tensile stress produced at chip ends of the semiconductor element when a covering film such as an oxide film is formed on the non-lamination portion of the solid-state imaging element and on an entire surface including the peripheral side surface of the semiconductor element on a side opposite to a lamination surface.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile