logo

For the Inventor, By the Inventor

Haifa, Israel

Tarek Rohana

This inventor holds 10 USPTO granted patents. Top assignee: Marvell Israel (Misl) Ltd.. Active years: 2012-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tarek Rohana. Retrieved from https://idiyas.com/inventor/tarek-rohana

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10

% Patents Active = 80.0

Average Co-Inventor Count = 2.1

ph-index = 3

Forward Citations = 46(Granted Patents)


Location History:

  • Haifa, IL (2012 - 2015)
  • Santa Clara, CA (US) (2015 - 2018)

Company Filing History:

goldMedal10 out of 608 
 
Marvell Israel (Misl) Ltd.
 patents

Years Active: 2012-2018

Loading Chart...
10 patents (USPTO):Explore Patents
1. RE46766 - Cache pre-fetch architecture and method (2018-03-26),
2. 8954681 - Multi-stage command processing pipeline and method for shared cache access (2015-02-10),
3. 8938585 - Transparent processing core and L2 cache connection (2015-01-20),
4. 8688911 - Transparent processing core and L2 cache connection (2014-04-01),
5. 8688886 - Bus transaction maintenance protocol (2014-04-01),
6. 8499123 - Multi-stage pipeline for cache access (2013-07-30),
7. 8484421 - Cache pre-fetch architecture and method (2013-07-09),
8. 8332590 - Multi-stage command processing pipeline and method for shared cache access (2012-12-11),
9. 8250280 - Bus transaction maintenance protocol (2012-08-21),
10. 8117395 - Multi-stage pipeline for cache access (2012-02-14),

Title: Tarek Rohana: Innovator in Cache Architecture

Introduction

Tarek Rohana is a prominent inventor based in Haifa, Israel, known for his significant contributions to the field of cache architecture. With a total of 10 patents to his name, he has made remarkable advancements in processing technologies that enhance system performance.

Latest Patents

Among his latest patents is the "Cache pre-fetch architecture and method." This invention provides a system on a chip (SOC) that includes a processing core and a cache with a cache instruction port, a cache data port, and port utilization circuitry. This circuitry is designed to selectively fetch and pre-fetch instructions, optimizing the efficiency of data processing. Another notable patent is the "Multi-stage command processing pipeline and method for shared cache access." This innovation features a command processing pipeline that is coupled to a shared cache, allowing for the independent processing of cache commands across different stages, thereby improving overall processing speed and resource utilization.

Career Highlights

Tarek Rohana is currently employed at Marvell Israel Ltd., where he continues to develop cutting-edge technologies in the field of cache architecture. His work has been instrumental in advancing the capabilities of modern computing systems.

Collaborations

Tarek collaborates with talented professionals in his field, including Gil Stoler and Yuval Avnon. Their combined expertise contributes to the innovative projects at Marvell Israel.

Conclusion

Tarek Rohana's contributions to cache architecture and processing technologies have established him as a key figure in the field. His patents reflect a commitment to innovation that continues to shape the future of computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…