Multi-stage pipeline for cache access

Abstract

Some of the embodiments of the present disclosure provide a command processing pipeline to be operatively coupled to a shared cache, the command processing pipeline comprising a command processing pipeline operatively coupled to the N-way cache and configured to process a sequence of cache commands, wherein a way of the N ways of the cache with which an address of a cache command matches is a hit way for the cache command in case the cache command is a hit. In one embodiment, the command processing pipeline may be configured to receive a first cache command from one of the plurality of processing cores, select a way, from the N ways, as a potential eviction way, and generate, based at least in part on the received first cache command, N selection signals corresponding to the N ways, wherein each selection signal is indicative of whether the corresponding way is (A). the hit way and/or the eviction way, or (B). neither the hit way nor the eviction way. Other embodiments are also described and claimed.